16 nanometer


Semiconductor manufacturing
processes

The 16 nanometer (16 nm) node is the technology node following the 22 nm node. The exact naming of the technology nodes comes from the International Technology Roadmap for Semiconductors (ITRS). By conservative ITRS estimates the 16 nm technology is projected to be reached by semiconductor companies in the 2018 timeframe. It has been claimed that transistors cannot be scaled below the size achievable at 16 nm due to quantum tunneling, regardless of the materials used.[1] As of 2009, leading companies are working on 22 nm development. However, in complying with its own "Architecture and Silicon Cadence Model",[2] Intel will need to reach a new manufacturing process every two years; this would imply going to 16 nm node as early as 2013. However, for Intel the design rule at this node designation is actually about 30 nm.[3]

16 nm resolution is difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 50 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and possibly iterated double patterning will be required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,[4] but can also go up to about 100 nm.[5] The damage sensitivity is expected to get worse as the low-k materials become more porous.

Currently, very few 16 nm features are capable of being produced using reliable processes in mass quantity, with some notable attempts like carbon nanotubes. Even in these cases, the variation within any sample population is quite large and the compatibility of such exotic processes and materials with current mainstream ones present further issues.

For comparison, the lattice constant, or distance between surface atoms, of unstrained silicon is 543 pm (0.543 nm). Thus fewer than thirty atoms would span the channel length, leading to substantial leakage.

Because exotic technologies not based on silicon are expected to become prominent during this node, and at the same time conventional silicon technology is still being pushed to the scaling limits, this node can be seen as a transition from CMOS to nanoelectronics.

Technology demos

In 2005 Toshiba demonstrated 15 nm gate length and 10 nm fin width using a sidewall spacer process.[6] It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.[1]

In December 2007, Toshiba demonstrated a prototype memory unit which uses 15 nanometer thin lines. [7]

References

  1. ^ a b "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003. http://news.zdnet.com/2100-9584_22-5112061.html. 
  2. ^ ¿â¾�Îô9{Aß8”Ò ª. "Intel Architecture and Silicon Cadence – The Catalyst for Industry Innovation". Intel White Paper. Archived from the original on 2009-05-02. http://www.webcitation.org/5gTsC3JMM. Retrieved on 2009-04-17. 
  3. ^ Y. Borodovsky, "Marching to the beat of Moore's Law," Proc. SPIE 6153 (2006).
  4. ^ O. Richard et al., Microelectronic Engineering 84, pp. 517-523 (2007).
  5. ^ T. Gross et al., Microelectronic Engineering 85, pp. 401-407 (2008).
  6. ^ Kaneko, A; A Yagashita, K Yahashi, T Kubota, et al. (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005): 844-847. doi:10.1109/IEDM.2005.1609488. 
  7. ^ 15 nanometre memory tested - The INQUIRER


Preceded by
22 nm		 CMOS manufacturing processes Succeeded by
11 nm


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